Program:
12.30-13.30 welcome
13.30-14.00 Device architecture changes: planar->FinFETs -> Nanosheets -> CFET: Devin Verreck
14.00-14.30 Evolution of lithography for logic scaling from 248nm to highNA EUV: Kurt Ronse, Progam Director
14.30-15.00 DTCO and STCO: Fernando Garcia, Principal Member of Technical Staff
15.00-15.30 Packaging and System Integration Readiness for Mobile genAI by Joshua A. H. Klein, Researcher SID
15.30-16.00 visit to the cleanroom
Bldg: Imec Tower, Remisebosweg 1 , Heveree, Vlaams Brabant, Belgium, 3001
